1. Field of the Invention
The present invention relates to a multi-layer capacitor and, more particularly, to a multi-layer capacitor that is constructed for use in high-frequency circuits.
2. Description of the Related Art
The most common multi-layer capacitor conventionally available is constructed of a ceramic dielectric material, for example, and includes a plurality of dielectric layers laminated with an internal electrode disposed therebetween. To construct a plurality of capacitors, a plurality of pairs of first and second internal electrodes are laminated with particular dielectric layers sandwiched therebetween in the direction of lamination. A capacitor is constructed in this manner.
First and second external terminal electrodes are respectively disposed on first and second end surfaces of the capacitor body. The first internal electrode has a lead extending to the first end surface of the capacitor body, and the lead is electrically connected to the first external terminal electrode. The second internal electrode has a lead extending to the second end surface of the capacitor body, and the lead is electrically connected to the second external terminal electrode.
In such a multi-layer capacitor, a current flows from the second external terminal electrode to the first external terminal electrode. More specifically, the current flows from the second external terminal electrode to the second internal electrode, and flows to the first internal electrode via a dielectric layer from the second internal electrode, and finally reaches the first external terminal electrode via the first internal electrode.
The equivalent circuit of the capacitor is a serial connection of C, L and R, where C represents the capacitance of the capacitor, L represents an equivalent series inductance (ESL), and R represents an equivalent resistance (ESR) which is mainly the resistance of the electrodes.
The equivalent circuit of the capacitor has a resonance frequency of f0=1/[(2xcfx80(LC)xc2xd], and cannot work as a capacitor in a frequency range above the resonance frequency. In other words, the smaller the inductance L, more specifically ESL, is, the higher the resonance frequency fO becomes, and the capacitor accordingly can work on a higher frequency. Although constructing the internal electrode of copper to reduce ESR is contemplated, a capacitor having a small ESL is required if it is intended for use in a microwave range.
A low ESL is also required of a capacitor which is used as a decoupling capacitor connected to a power supply circuit which feeds power to a microprocessing unit (MPU) chip for use in a work station or a personal computer.
FIG. 15 is a block diagram showing an example of the configuration of the above-referenced MPU 31 and a power supply 32.
Referring to FIG. 15, MPU 31 includes an MPU chip 33 and a memory 34. The power supply 32 feeds power to the MPU chip 33. A decoupling capacitor 35 is connected in the power line that extends from the power supply 32 to the MPU chip 33. Signal lines are formed between the MPU chip 33 and the memory circuit 34.
Like an ordinary decoupling capacitor, the decoupling capacitor 35, associated with MPU 31, is used to absorb noise and smooth fluctuations in power supply voltage. Recently, the MPU chip 33 has an operating frequency of 500MHz or higher, and some chips reaching an operating frequency of 1 GHz are currently under development. In high-speed applications keeping pace with such an MPU chip 33, a quick power supply function is required of the capacitor. The quick power supply function is to feed power from the electricity stored in a capacitor within several nanoseconds when power is instantaneously required, such as during startup.
The MPU 31 thus needs a decoupling capacitor 35 having an inductance that is as low as possible, for example, 10 pH or lower. A capacitor having such a low inductance is therefore required for such a decoupling capacitor.
An MPU chip 33 having an operating clock frequency of 450 MHz is supplied with 1.8 volts to 2.0 volts DC, and its power consumption is 23 W, i.e., with a current of 12 A drawn. To reduce power consumption, the MPU 31 is set to operate in a sleep mode at a power consumption of 1W when it is not being used. When the MPU 31 is changed from the sleep mode to the active mode, the MPU chip 33 needs to be supplied with enough power for the active mode to start within several clock pulses. At the operating clock frequency of 450 MHz, power must be supplied within 4 to 7 nanoseconds when the sleep mode is switched to the active mode.
Since the power feeding from the power supply 32 is not fast enough, the charge stored in the decoupling capacitor 35 is placed in the vicinity of the MPU chip 33 is first discharged to feed power to the MPU chip 33 until the power feeding from the power supply 32 starts.
At an operating clock frequency of 1 GHz, the ESL of the decoupling capacitor 35 located in the vicinity of the MPU chip 33 needs to be 10 pH or smaller for the decoupling capacitor 35 to function in the manner described above.
The ESL of typical multi-layer capacitors ranges from 500 to 800 pH, which is far from the above-referenced value of 10 pH. Such an inductance component is created in the multi-layer capacitor because a magnetic flux, the direction of which is determined by a current flowing through the multi-layer capacitor, is created, and a self inductance is created due to the magnetic flux.
Under these situations, the structures of multi-layer capacitors that can achieve a low ESL have been proposed in U.S. Pat. No. 5,880,925, Japanese Unexamined Patent Publication 2-159008 and Japanese Unexamined Patent Publication No. 7-201651.
The above disclosed method of achieving a low ESL is heavily dependent on the cancellation of magnetic fluxes induced in the multi-layer capacitor. To cancel magnetic fluxes, the direction of a current flowing in the multi-layer capacitor is diversified. To diversify the direction of the current, the number of terminal electrodes disposed on the external surface of the capacitor body is increased so that the number of leads of internal electrodes connected to the respective external terminal electrodes is increased. At the same time, the leads of the internal electrodes are aligned in several directions.
The effectiveness of the proposed method of achieving a low ESL in the multi-layer capacitor is not sufficient.
For example, U.S. Pat. No. 5,880,925 and Japanese Unexamined Patent Publication No. 2-159008 discloses a structure in which the leads of internal electrodes extend to opposing sides of a capacitor body. It is estimated that such a structure achieves a low ESL of about 100 pH.
In order to overcome the problems described above, preferred embodiments of the present invention provide a multi-layer capacitor that has been improved to further effectively reduce ESL, to achieve a higher resonance frequency, to achieve a more compact device, to obtain a higher capacitance than previously was possible with conventional devices and to improve the ease of mounting of the capacitor.
These and other advantages are achieved by various preferred embodiments of the present invention.
For example, according to one preferred embodiment of the present invention, a multi-layer capacitor has a substantially square-shaped ceramic body including four sides having substantially equal dimensions and a plurality of external electrode terminals disposed on each of the four sides of the substantially square-shaped ceramic body.
It should be noted that the substantially square-shaped ceramic body and configuration of external electrode terminals in a manner that is symmetrical on each of the four sides, the capacitor can be mounted in any orientation on an electrode pattern provided on a printed circuit board. As a result, it is not necessary to accurately position and orient the capacitor on the printed circuit board, and thus, mounting of the capacitor is greatly simplified.
According to another preferred embodiment of the present invention, there are at least two of the external electrode terminals provided on each of the four sides of the substantially square-shaped ceramic body.
There may be two or more external electrode terminals disposed on each of the four sides of the substantially square-shaped body.
Further, in some preferred embodiments, only one pair or both pairs of opposite sides of the substantially square-shaped ceramic body may have an even number of external terminals. Alternatively, only one pair or both pairs of opposite sides of the substantially square-shaped ceramic body may have an odd number of external terminals.
It should also be noted that all four sides of the substantially square-shaped ceramic body may have an equal number of external electrodes, either odd or even in number. Alternatively, a first of the pair of opposite sides of the substantially square-shaped ceramic body may have an odd number of external electrodes and the other of the pair of opposite sides of the substantially square-shaped ceramic body may have an even number of external electrodes.
As will be described in more detail below, it is preferred that each of the external electrode terminals be disposed directly opposite to one of the external electrode terminals located on an opposite side of the substantially square-shaped ceramic body, across the substantially square-shaped ceramic body, to define respective pairs of directly oppositely disposed external electrode terminals. It is also preferred that each of the respective pairs of directly oppositely disposed external electrode terminals include a first polarity external electrode terminal and a second polarity external electrode terminal. That is, it is preferred that the external electrode terminals which are directly opposite to each other across the ceramic body have opposite polarities.
It should be noted that with respect to the above-described preferred embodiments, the external electrode terminals are electrically connected to respective lead out portions which extend from respective internal electrodes. The internal electrodes are opposed to each other in the substantially-square ceramic body with dielectric layers disposed therebetween.
The internal electrodes are arranged to define respective ones of a first polarity electrode including first polarity lead out portions and a second polarity electrode including second polarity lead out portions. The first polarity lead out portions extend from a main portion to edges of the substantially-square ceramic body and are electrically connected to respective ones of the first polarity external electrode terminals. The second polarity lead out portions extend from a main portion to edges of the substantially-square ceramic body and are electrically connected to respective ones of the second polarity external electrode terminals.
It should be noted that the arrangement of the first and second polarity lead-out portions correspond to the above-described arrangement of the corresponding ones of the first and second polarity external electrode terminals.
Also, it is preferred that the first polarity lead-out portions and the second polarity lead-out portions have the same dimensions including length and width. Further, it is preferred that the dimensions including length and width of main portions of the first and second polarity internal electrodes have the same shape and configuration.
According to yet another preferred embodiment of the present invention, a multi-layer capacitor includes a capacitor body that has a substantially quadrangular body defined by a dimension in a length direction, a dimension in a width direction, and a dimension in a thickness direction, the dimension in the length direction and the dimension in the width direction being substantially identical, the capacitor body having opposing first and second major surfaces defined by the dimension in the length direction and the dimension in the width direction, and having opposing first and second side surfaces defined by the dimension in the length direction and the dimension in the thickness direction, and opposing first and second end surfaces defined by the dimension in the width direction and the dimension in the thickness direction.
The capacitor body is provided with a plurality of dielectric layers extending toward the major surfaces and at least a pair of first and second internal electrodes that oppose each other via a particular one of the dielectric layers to define a capacitor unit. Each of the first and second internal electrodes has a substantially square pattern that includes sides extending substantially parallel to the first and second side surfaces, and the first and second end surfaces, respectively, of the capacitor body.
The first internal electrode has first lead-out portions that extend onto the first and second side surfaces and onto the first and second end surfaces. First external electrode terminals which are electrically connected to the first lead-out portions are provided on the first and second side surfaces and the first and second end surfaces, respectively, where the first lead-out portions are extended and exposed.
Furthermore, the second internal electrode has second lead-out portions that are extended onto the first and second side surfaces and onto the first and second end surfaces. Second external electrode terminals which are electrically connected to the second lead-out portions are provided on the first and second side surfaces and the first and second end surfaces, respectively, where the second lead-out portions are extended and exposed.
The first external electrode terminal and the second external electrode terminal are alternately disposed on the first and second side surfaces and the first and second end surfaces, respectively, and arranged such that opposite polarity terminals are directly opposite to each other across the capacitor body.
In one preferred embodiment of the present invention, each of the first and second side surfaces and each of the first and second end surfaces is provided with a plurality of first and second lead-out portions and first and second external electrode terminals.
In another preferred embodiment of the present invention, each of the first and second side surfaces and each of the first and second end surfaces is provided with a total of four or less of the first and second lead-out portions and the first and second external electrode terminals.
In another preferred embodiment of the present invention, a plurality of opposing portions of the first internal electrodes and the second internal electrodes are arranged to define a plurality of capacitor units connected in parallel by the first and second external electrode terminals.
Other features, elements, advantages and aspects of the present invention will be described in the following detailed description of preferred embodiments of the present invention with reference to the attached drawings, wherein like reference numerals indicate like elements.